library IEEE;
use IEEE.std_logic_1164.all;

entity reg_alu_to_vrf is
	port (
		D_i   : in std_logic_vector (3 downto 0);
		CLK_i : in std_logic;
		Q_o   : out std_logic_vector (3 downto 0) );
end reg_alu_to_vrf;

architecture behavioral of reg_alu_to_vrf is
begin 
	process ( CLK_i )
	begin
		if CLK_i = '1' and CLK_i'EVENT then
			Q_o <= D_i;
		end if;
	end process;
end behavioral;
